The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for forming a storage node contact plug in a semiconductor device.
In storage node contact plugs with a feature size of less than 80 nm, the large scale of integration in semiconductor devices have led to formation of hole type contacts using ArF photoresist.
FIG. 1 is a top view illustrating a typical semiconductor device.
A plurality of gate lines 13 are arranged on active regions 11A in one direction. A plurality of landing plug contacts 15 are formed on the respective active regions 11A between the gate lines 13. A plurality of bit lines BL are arranged perpendicular to the gate lines 13 to be connected with a group of the landing plug contacts 15. A plurality of storage node contact plugs SNC are formed on the landing plug contacts 15 in a region where the bit lines BL and the gate lines 13 cross with each other. A plurality of storage nodes SN are formed on the storage node contact plugs SNC.
FIG. 2 is a cross-sectional view illustrating the typical semiconductor device taken along the line I-I′ of FIG. 1. FIG. 3 is a cross-sectional view illustrating the typical semiconductor device taken along the line II-II′ of FIG. 1.
Referring to FIGS. 2 and 3, device isolation layers (not shown) are formed in predetermined areas of a substrate 11 to define the active regions 11A. The plurality of the gate lines 13 (see FIG. 1) are formed on the substrate 11, and gate line spacers are formed on the sidewalls of the gate lines 13.
A first inter-layer insulation layer 14 is formed on the gate lines 13 and planarized thereafter. The first inter-layer insulation layer 14 is etched to form contact holes (not shown) which expose the active regions 11A between the gate lines 13. Then the landing plug contacts 15 are formed on the active regions 11A.
A second inter-layer insulation layer 16 is formed on the landing plug contacts 15 and the first inter-layer insulation layer 14, and a plurality of bit line patterns 100 are formed on the second inter-layer insulation layer 16. Each of the bit line patterns 100 includes a barrier metal layer 17, a bit line tungsten layer 18 and a bit line hard mask nitride layer 19, which are formed in sequential order. The barrier metal layer 17 is obtained by sequentially forming TiN and Ti.
Bit line spacers 20 are formed on the sidewalls of the bit line patterns 100. A third inter-layer insulation layer 21 is formed on the bit line patterns 100 until the third inter-layer insulation layer 21 fills spaces between the bit line patterns 100. Hole type storage node contact masks 22 are formed on the third inter-layer insulation layer 21.
Using the storage node contact masks 22 as an etch mask, the third inter-layer insulation layer 21 and the second inter-layer insulation layer 16 are etched to form storage node contact holes 23, which expose the surface of the landing plug contacts 15. This etching process for forming the storage node contact holes 23 employs a self-aligned contact (SAC) etching process.
Although not illustrated, storage node contact plugs SNC are formed by filling the storage node contact holes 23 with a polysilicon layer using a plug isolation process. The storage nodes SN are then formed on the storage node contact plugs SNC.
However, since the storage node contact plugs are formed in the storage node contact holes, the open area at the top part of each of the storage node contact plugs is generally small. Thus, the overlay margin for the storage nodes becomes too small, requiring the formation of a pad polysilicon layer between the storage node contact plugs and the storage nodes.
When the etching process for forming the storage node contact holes is performed, an ArF photoresist material is often used. For this process, an expensive etching apparatus is generally used increasing the maintenance cost, thereby impeding mass production. Also, during the etching process for forming the storage node contact holes, the bit line hard mask layer is more likely to be damaged and this damage is denoted with reference numeral 24 in FIG. 2. The damage to the bit line hard mask layer may cause SAC failures such as a short circuit between the storage nodes and the storage node contact plugs.